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| Model 658 CLOCK, HIGH FREQUENCY MULTIPLIER FEATURES * * * * * * * * * * Standard 7x5mm Surface Mount Footprint LVCMOS, Differential LVPECL or LVDS Outputs Frequency Range 38 - 750 MHz Frequency Stability, 50 ppm Standard ( 25 ppm and 100 ppm available) +2.5Vdc or +3.3Vdc Operation Operating Temperature to -40C to +85C Output Enable Standard Low Phase Jitter, PLL Multiplier Tape & Reel Packaging RoHS/Green Compliant DESCRIPTION The Model 658 is a ceramic packaged Clock oscillator offering reduced size and enhanced stability. The small size means it is perfect for any application. The enhanced stability means it is the perfect choice for today's communications applications that require tight frequency control. ORDERING INFORMATION 658 OUTPUT TYPE C = CMOS, Pin 1 Enable Pin 2 N.C. (standard) L = LVDS, Pin 1 Enable Pin 2 N.C. (standard) P = PECL, Pin 1 Enable Pin 2 N.C. (standard) M = CMOS, Pin1 N.C. Pin 2 Enable V = LVDS, Pin1 N.C. Pin 2 Enable E = PECL, Pin1 N.C. Pin 2 Enable FREQUENCY STABILITY 5 = 25 ppm 3 = 50 ppm (standard) 2 = 100 ppm M FREQUENCY IN MHz M - indicates MHz and decimal point. Frequency is recorded with minimum 4 significant digits to the right of the "M". SUPPLY VOLTAGE 2 = 2.5 Vdc (LVDS and PECL only) 3 = 3.3 Vdc OPERATING TEMPERATURE RANGE C = 0C to +70C (standard) I = -40C to +85C Example Part Number: 658P3C3155M5200 Document No. 008-0316-0 Page 1 - 5 Rev. A CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108 www.ctscorp.com 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock Model 658 ELECTRICAL CHARACTERISTICS PARAMETER Maximum Supply Voltage Absolute Maximums Storage Temperature Frequency Range LVCMOS LVPECL and LVDS (See Note 1 and Ordering Information) SYMBOL VCC TSTG fO f/fO TA VCC 5% CONDITIONS - MIN -0.5 -55 50 38 0 -40 2.38 3.14 < 160 MHz 160 MHz 0.7*VCC - TYP - MAX 7.0 125 250 750 25, 50 or 100 70 85 2.63 3.47 40 50 75 100 60 80 10 5 0.3*VCC 20 10 15 55 10%VCC 5.0 55 VCC - 1.62V 1.0 55 450 1.6 1.0 UNIT V C MHz Frequency Stability - ppm C Operating Temperature Commercial Industrial (See Ordering Information) 25 2.5 3.3 3.5 5 2 50 0.4 Supply Voltage Supply Current LVCMOS LVPECL LVDS Start Up Time Phase Jitter V Maximum Load ICC < 160 MHz 160 MHz < 160 MHz 160 MHz mA TS tjms VIH VIL IIL TPLZ CL SYM VOH VOL TR, TF RL SYM VOH VOL TR, TF RL SYM VOD VOH VOL TR, TF Application of VCC Bandwidth 12 kHz - 20 MHz Pin 1 or Pin 2 Logic '1', Output Enabled Pin 1 or Pin 2 Logic '0', Output Disabled Pin 1 or Pin 2 Logic '1' , Output Disabled Pin 1 or Pin 2 Logic '1' ms ps RMS V uA ms pF % V ns Ohms % V ns Ohms % mV V ns Enable Function Enable Input Voltage Electrical and Waveform Parameters Disable Input Voltage Disable Current Enable Time LVCMOS WAVEFORM Output Load Output Duty Cycle Output Voltage Levels Logic '1' Level Logic '0' Level Rise and Fall Time LVPECL WAVEFORM Output Load Output Duty Cycle Output Voltage Levels Logic '1' Level Logic '0' Level Rise and Fall Time LVDS WAVEFORM Output Load Output Duty Cycle Differential Voltage Output Voltage Levels Logic '1' Level Logic '0' Level Rise and Fall Time @ 50% Level CMOS Load CMOS Load @ 20% - 80% Levels @ VCC - 1.3V PECL Load PECL Load @ 20% - 80% Levels @ 1.25V RL = 100 Ohms LVDS Load LVDS Load @ 20% - 80% Levels 45 90%VCC 45 VCC - 1.025V - 45 250 0.9 - 100 350 0.4 Notes: 1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging at an average operating temperature of +40 C. Document No. 008-0316-0 Page 2 - 5 Rev. A CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock CMOS/TTL OUTPUT WAVEFORM TEST CIRCUIT, CMOS LOAD Model 658 Tr Tf N.C. VOH 90%, 80%, 2.4V + mA - 6 5 D.U.T. 4 CL 3 Including probe capacitance. 50%, 1.5V + POWER SUPPLY + VM - 0.01uF 10%, 20%, 0.5V UPTIME (t) PERIOD (T) - 1 2 VOL DUTY CYCLE = t/T x 100 (%) Enable Input or N.C. N.C. or Enable Input PECL/LVDS OUTPUT WAVEFORM Tr Tf TEST CIRCUIT, PECL LOAD Vcc - 2.0V OUT VOH 80% RL 50 CH2 VOS 50% + mA RL 50 Vcc - 2.0V 3 CH1 6 5 D.U.T. 1 2 4 20% OUT UPTIME (t) PERIOD (T) + POWER SUPPLY + VM - 0.01uF VOL - DUTY CYCLE = t/T x 100 (%) Enable Input or N.C. N.C. or Enable Input TEST CIRCUIT, LVDS LOAD D.U.T. PIN ASSIGNMENTS PIN 1 2 3 4 5 6 SYMBOL EOH / NC NC / EOH GND Output Output / NC VCC DESCRIPTION Enable or No Connect No Connect or Enable Circuit & Package Ground RF Output Complimentary RF Output (PECL and LVDS Only) CH2 RL 100 CH1 6 + POWER SUPPLY + mA - 5 D.U.T. 4 + VM - 0.01uF Supply Voltage - 1 2 3 ENABLE TRUTH TABLE PIN 1 or 2 Logic `1' Open Logic `0' PIN 4 / PIN 5 Output Output High Imp. Enable Input or N.C. N.C. or Enable Input Document No. 008-0316-0 Page 3 - 5 Rev. A CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock Model 658 MECHANICAL SPECIFICATIONS PACKAGE DRAWING (7.0 0.2) 0.276 0.008 PIN 1 IDENTIFIER (1.4) 0.055 (1.27) 0.050 (5.0 0.2) 0.197 0.008 (3.73) 0.147 4 5 6 MARKING INFORMATION 1. 2. 3. 4. ** - Manufacturing Site Code. YYWW - Date code, YY - year, WW - week. Truncated CTS part number. XXXMXXXX - Frequency marked with 4 significant digits after the `M'. CTS ** YYWW 658P3C3 XXXMXXXX 3 2 1 (2.54) 0.100 (2.0) MAX 0.079 (5.08) 0.200 Key: (mm) Inch NOTES 1. Termination pads (e4), barrier-plating is nickel (Ni) with gold (Au) flash plate. 2. Reflow conditions per JEDEC J-STD-020. SUGGESTED SOLDER PAD GEOMETRY .071 [1.80] 300 SUGGESTED REFLOW PROFILE C BYPASS 6 5 4 200 Maximum 260C, 10 seconds Typical 245C .165 [4.20] Temp. (C) 100 130C .079 [2.00] 1 2 .100 [2.54] .200 [5.08] [mm] Key: Inch 3 0 0 30 60 90 120 150 180 210 240 270 300 Time (Seconds) CBYPASS should be 0.01 uF. Document No. 008-0316-0 Page 4 - 5 Rev. A CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108 7x5mm Low Cost LVCMOS, LVPECL or LVDS Clock Model 658 TAPE AND REEL INFORMATION DIMENSIONS IN MILLIMETERS 17.5 O13 4.0 8.0 O1.50 1.75 2.40 2.10 2.0 120 8.40 7.90 16.0 O60 O180 5.70 5.40 DIRECTION OF FEED O23 Device quantity is 1,000 pieces per 180mm reel. ENVIRONMENTAL SPECIFICATIONS Temperature Cycle: Mechanical Shock: Sinusoidal Vibration: Gross Leak: Fine Leak: Resistance to Solder Heat: High Temperature Operating Bias: Frequency Aging: Moisture Sensitivity Level: 400 cycles from -55C to +125C, 10 minute dwell at each temperature, 1 minute transfer time between temperatures. 1,500g's, 0.5mS duration, 1/2 sinewave, 3 shocks each direction along 3 mutually perpendicular planes (18 total shocks). 0.06 inches double amplitude, 10 to 55 Hz and 20g's, 55 to 2,000 Hz, 3 cycles each in 3 mutually perpendicular planes (9 times total). No leak shall appear while immersed in an FC40 or equivalent liquid at +125C for 20 seconds. Mass spectrometer leak rates less than 2x10-8 ATM cc/sec air equivalent. Product must survive 3 reflows of +260C peak, 10 seconds maximum. 2,000 hours at +125C, maximum bias, disregarding frequency shift. 1,000 hours at +85C, full bias, less than 5 ppm shift. Level 1 per JEDEC J-STD-020. QUALITY AND RELIABILITY Quality systems meet or exceed the requirements of ISO 9000:2000 standards. Document No. 008-0316-0 Page 5 - 5 Rev. A CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108 |
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